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[Embeded-SCM Develop] SIN_fashengqi

Description: 2006altera大赛－基于软核Nios的宽谱正弦信号发生器设计：摘要：本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA公司的 Cyclone 系列 FPGA 为数字平台，将微处理器、总线、数字频率合成器、存储器和 I/O 接口等硬件设备集中在一片 FPGA 上，利用直接数字频率合成技术、数字调制技术实现所要求波形的产生，用 FPGA 中的 ROM 储存 DDS 所需的波形表，充分利用片上资源，提高了系统的精确度、稳定性和抗干扰性能。使用新的数字信号处理（DSP）技术，通过在 Nios 中软件编程解决 不同的调制方式的实现和选择。系统频率实现 1Hz～20MHz 可调，步进达到了1Hz；完成了调幅、调频、二进制 PSK、二进制 ASK、二进制 FSK 调制和扫频输出的功能。 -2006altera race-based soft-core Nios wide spectrum of sinusoidal signal generator design : Abstract : The use of design-based Nios II embedded processor SOPC technology. Altera Corporation system to the Cyclone FPGA series of digital platform, microprocessor, bus, Digital Frequency Synthesizer, memory and I / O interface hardware concentrated in an FPGA, the use of direct digital frequency synthesis technology and digital modulation waveforms required to achieve the rise, Using FPGA ROM storage of the DDS waveform table, and make full use of on-chip resources, improve the system's accuracy, stability and robustness. Use of new digital signal processing (DSP) technology, Nios through software programming to solve different ways of achieving modulation and choice. Realize the system freq
Platform: | Size: 407706 | Author: 刘斐 | Hits:

[Embeded-SCM Develop] Cyclone1C20的Nios开发板完整原理图Protel格式

Description: Cyclone1C20的Nios开发板完整原理图Protel格式，很有参考价值 --The complete design of CycloneC20 s Nios development. It is in Protel format and is a valuable reference.
Platform: | Size: 77824 | Author: | Hits:

[Embeded-SCM Develop] SIN_fashengqi

Description: 2006altera大赛－基于软核Nios的宽谱正弦信号发生器设计：摘要：本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA公司的 Cyclone 系列 FPGA 为数字平台，将微处理器、总线、数字频率合成器、存储器和 I/O 接口等硬件设备集中在一片 FPGA 上，利用直接数字频率合成技术、数字调制技术实现所要求波形的产生，用 FPGA 中的 ROM 储存 DDS 所需的波形表，充分利用片上资源，提高了系统的精确度、稳定性和抗干扰性能。使用新的数字信号处理（DSP）技术，通过在 Nios 中软件编程解决 不同的调制方式的实现和选择。系统频率实现 1Hz～20MHz 可调，步进达到了1Hz；完成了调幅、调频、二进制 PSK、二进制 ASK、二进制 FSK 调制和扫频输出的功能。 -2006altera race-based soft-core Nios wide spectrum of sinusoidal signal generator design : Abstract : The use of design-based Nios II embedded processor SOPC technology. Altera Corporation system to the Cyclone FPGA series of digital platform, microprocessor, bus, Digital Frequency Synthesizer, memory and I/O interface hardware concentrated in an FPGA, the use of direct digital frequency synthesis technology and digital modulation waveforms required to achieve the rise, Using FPGA ROM storage of the DDS waveform table, and make full use of on-chip resources, improve the system's accuracy, stability and robustness. Use of new digital signal processing (DSP) technology, Nios through software programming to solve different ways of achieving modulation and choice. Realize the system freq
Platform: | Size: 407552 | Author: 刘斐 | Hits:

[Embeded-SCM Develop] CycloneIII_SB_3C25

Description: Altera CycloneIII_Starter_Kit 开发板原理图-Altera CycloneIII_Starter_Kit development board schematics
Platform: | Size: 264192 | Author: | Hits:

[Embeded-SCM Develop] sdsdi

Description: DVB系统的SDI数据数据传输接口，FPGA设计实现-DVB system SDI data transmission interface, FPGA Design and Implementation
Platform: | Size: 229376 | Author: 梁光辉 | Hits:

[Other Embeded program] CycloneII_Touch_Panel_MP3_Player

Description: 在SOPC平台上，开发得MP3源代码，包括mp3软解码，图形界面！还包括了TFT,PWM的IP!-In SOPC platform, the development of a MP3 source code, including mp3 soft decoding, graphical interface! Also includes a TFT, PWM s IP!
Platform: | Size: 1692672 | Author: lrt | Hits:

[VHDL-FPGA-Verilog] psk

Description: 利用VHDL语言实现在，altera 公司的cyclone芯片上实现数字信号的2psk调制解调功能-The use of VHDL language to achieve, altera s cyclone chip digital signal modulation and demodulation functions 2psk
Platform: | Size: 293888 | Author: 叶峰 | Hits:

[SCM] Board

Description: ALtera FPGA Cyclone III开发电路图，对初学者设计此类FPGA有重要参考价值-ALtera FPGA Cyclone III development of schematics, such FPGA design for beginners have important reference value
Platform: | Size: 3165184 | Author: sky | Hits:

[VHDL-FPGA-Verilog] TrackingPresentation_jon

Description: presentation a low cost video tracking algorithm implemented on an Altera DE2 board with Cyclone II processor. System uses a VGA controller and several SG-DMA s-presentation on a low cost video tracking algorithm implemented on an Altera DE2 board with Cyclone II processor. System uses a VGA controller and several SG-DMA s
Platform: | Size: 1514496 | Author: stjohn | Hits:

[Communication-Mobile] irig

Description: irig-b 单片机 解析 MSP430系列单片机是集成度高、超低功耗的16位单片机。Cyclone系列芯片是Altera公司推出的低价格、RAM可达288 kb的高容量的FPGA。IRIG-B码广泛应用于靶场时间信息的传递和各系统的时间同步。详细介绍了IRIG-B码解码电路和调制电路的硬件设计。MSP430的软件采用C语言编写，使程序有很强的可移植性。-irig-b microcontroller MSP430 Microcontroller analysis are highly integrated, ultra-low-power 16-bit microcontroller. Altera' s Cyclone series of chips are launched in low-cost, RAM up to 288 kb of high-capacity FPGA. IRIG-B time code range is widely used in the transmission of messages and the system time synchronization. Details of the IRIG-B decoding circuit and modulation circuit of the hardware design. MSP430 software using C language, so that programs are highly portable.
Platform: | Size: 11264 | Author: JEFF | Hits:

[VHDL-FPGA-Verilog] cyclone_handbook

Description: Altera 公司生产的FPGA系列中的低端高性能产品cyclone一代用户手册,这个也能从Altera官方网站上下载。-Altera' s FPGA series production of low-end high-performance products cyclone generation, user manuals, this is also downloaded from the Altera website.
Platform: | Size: 3013632 | Author: carris | Hits:

[VHDL-FPGA-Verilog] cyclone2_handbook

Description: Altera 公司生产的FPGA系列中的低端高性能产品cyclone二代用户手册,这个也能从Altera官方网站上下载。-Altera' s FPGA series production of low-end high-performance products cyclone II user' s manual, this is also downloaded from the Altera website.
Platform: | Size: 3330048 | Author: carris | Hits:

[VHDL-FPGA-Verilog] FPGA_Clk

Description: 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other modules. The use of the timer-generated clock waveform. To provide for the FPGA clock even sub-frequency, odd-numbered sub-frequency, pulse width is always functions.
Platform: | Size: 1466368 | Author: icemoon1987 | Hits:

[Other] cycloneIII_useful_SCH

Description: cyclone III 原理图，很实用的原理图，找了很长时间才找到-cyclone III schematic, it is useful schematic, looking for a very long time to find
Platform: | Size: 64512 | Author: liqiang | Hits:

[VHDL-FPGA-Verilog] pci32tlite_oc_latest.tar

Description: pci32 taget core ip, The core has been designed to permit interface between a PCI Master and simple WHISBONE Slaves, and fitting into smallest FPGA (about 200 LC s in ALTERA CYCLONE II FPGA).-pci32 taget core ip, The core has been designed to permit interface between a PCI Master and simple WHISBONE Slaves, and fitting into smallest FPGA (about 200 LC' s in ALTERA CYCLONE II FPGA).
Platform: | Size: 7813120 | Author: shen | Hits:

[VHDL-FPGA-Verilog] Cyclone-FPGA-Family-Data-Sheet

Description: Cyclone FPGA Family 数据手册。讲述altera公司的FPGA的相关器件。主要用于选型。-Cyclone FPGA Family Data Sheet. Altera about the company' s FPGA-related devices. Mainly used for selection.
Platform: | Size: 700416 | Author: rokcy | Hits:

[VHDL-FPGA-Verilog] cyclone-handbook

Description: altera 的cyclone fpga手册，比较全面介绍了这款fpga芯片-the cyclone handbook of altera s fpga，specifically introduced this fpga chip
Platform: | Size: 3291136 | Author: | Hits:

[VHDL-FPGA-Verilog] MYCRC

Description: 由于altera公司的CRC生成和校验模块不支持本系统使用的Cyclone IV E系列FPGA，因此本文独立设计了CRC模块。该模块的接口与altera公司的CRC模块接口基本一致，能够对16位输入的数据流进行CRC校验码生成和校验。本文采用CRC-CCITT生成项，其表达式为：X16+X12+X5+X0。本模块需要startp信号及endp信号指示数据传输的起始及结束。本模块采用状态机设计，对于数据头和数据尾分别由不同的状态来处理。在本模块中，使用了for循环，这会消耗较多的FPGA资源，但暂时任未发现其他改进的方法。-Because altera company' s CRC generation and checking modules do not support the use of the system Cyclone IV E series FPGA, so this independent design of the CRC module. The module' s interface with the CRC module interface altera' s basically the same, capable of 16-bit input data stream of CRC generation and checking. In this paper, CRC-CCITT generation entry, its expression is: X16+ X12+ X5+ X0. This module requires startp signal and endp signal indicating the start and end of data transmission. This module is a state machine design, and data for the end of the first data were handled by different states. In this module, use the for loop, which consumes more FPGA resources, but temporarily did not find any other ways to improve.
Platform: | Size: 4096 | Author: 陈建 | Hits:

[File Format] Cyclone-PLL

Description: cyclone器件的锁相环实现技术，包括锁相环的具体应用方法和使用细节，对于锁相环的学习者是个很好的教材。-implementation techniques, including details of the methods and use of the specific application of phase-locked loop the cyclone device s phase-locked loop, PLL learner is a good textbook.
Platform: | Size: 4175872 | Author: 剑侠 | Hits:

[Technology Management] altera-soc-cyclone-V

Description: 针对altera公司的soc平台的开发流程，适用于友晶cyclone v SOC开发板。-Altera soc platform for the company' s development process for Terasic cyclone v SOC development board.
Platform: | Size: 1392640 | Author: xinfgu | Hits:
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